Highlights
  • Universal PCI interfaces compatible with 3.3-V and 5-V PCI signaling environments.
  • Dual USB 2.0 Controllers (Each has one EHCI and one OHCI, total are two EHCI and two OHCI)
  • Compliant with Universal Serial Bus Specification Revision 2.0 (data rate: 1.5/12/480 Mbps)
  • Six USB Ports (Four External + Two Internal)
  • Supports hyper-speed transfer mode.
Introduction

U2X2-PCI01 is Dual Channel USB 2.0 to PCI Host Adapter

U2X2-PCI01 is designed with two key components.

  • PCI-to-PCI Bridge (32bit/33Mhz)
  • PCI multi-function device consists of one OHCI host controller core for full-/low-speed signaling and one EHCI host controller core for high-speed signaling.

U2X2-PCI01 integrated 4 host controller cores with PCI interface and USB 2.0 transceivers into a single PCI host adapter.

The PCI-to-PCI Bridge that are designed to be fully compliant with the 32-bit, 33MHz implementation of the PCI Local Bus Specification, Revision 2.2. Two PCI multi-function devices are integrated at the Secondary Bus to provide more connectivity and performance.

U2X2-PCI01 complies with USB Revision 2.0 and OHCI (Open Host Controller Interface) specification for full/low-speed signaling, and Intel's EHCI (Enhanced Host Controller Interface) specification for high-speed signaling which can work up to 480Mbps.

U2X2-PCI01 supports hyper-speed transfer mode for asynchronous transfer in high-speed mode, and it can greatly improve data transfer rate for high-speed devices supporting bulk transfer, such as USB storage, scanner, printer, etc.

Technical Specifications

Primary PCI Host Bus

  • 32-bit 33MHz host interface compliant with the PCI Local Bus Specification, Revision 2.2
  • Universal PCI interfaces compatible with 3.3-V and 5-V PCI signaling environments.
  • Compliant with PCI-to-PCI Bridge Architecture Specification, Revision 1.1.
    • All I/O and memory commands
    • Type 1 to Type 0 configuration conversion
    • Type 1 to Type 1 configuration forwarding
    • Type 1 configuration write to special cycle conversion
  • Compliant with the Advanced Configuration Power Interface (ACPI) Specification.
  • Compliant with the PCI Power Management Specification, Revision 1.1.
  • Provides internal arbitration for four secondary bus masters
    • Programmable 2-level priority arbiter
    • Disable control for use of external arbiter
  • Supports posted write buffers in all directions
  • Four 128 byte FIFO.s for delay transactions
  • Two 128 byte FIFO.s for posted memory transactions
  • Enhanced address decoding
  • 32-bit I/O address range
  • 32-bit memory-mapped I/O address range
  • 64-bit prefetchable address range
  • ISA-aware mode for legacy support in the first 64KB of I/O address range  
Secondary PCI Host Bus
  • 32-bit 33MHz host interface compliant with the PCI Local Bus Specification, Revision 2.2
  • Supports PCI-bus power management interface specification release 1.1
  • PCI bus bus-master access
  • Operational registers direct-mapped to PCI memory space
  • Supports 3.3 V PCI

USB Feature

  • Compliant with universal serial bus specification revision 2.0
  • Compliant with open host controller interface specification for USB rev 1.0a
  • Compliant with enhanced host controller interface specification for USB revision 1.0
  • PCI multi-function device consists of one OHCI host controller core for full-/low-speed signaling and one EHCI host controller core for high-speed signaling
  • Root hub with 3 (Max.) downstream facing ports which are shared by OHCI and EHCI host controller cores
  • Supports hyper-speed transfer mode using HSMODE signal. Transfer rate is 1.5 times higher than existing host controllers
USB Data Transfer Rate:
  • Low-speed at 1.5Mbps
  • Full-Speed at 12Mbps
  • High-Speed at 480 Mbps
Number of Ports:
  • USB 1 : Two External + One Internal
  • USB 2 : Two External + One Internal
Computer Platform
  • Computer with PCI slot
Operating System Requirements

Native driver support in various operating system.

  • Windows 2000 SP4/XP SP1/2003/Vista
  • Mac OS
  • Linux kernel 2.4.19