• Host Bus: 1-lane 2.5 Gb/s PCI Express version 1.1
  • Multiple virtual channel (VC0,VC1 ) support for differentiating 1394 isochronous traffic.
  • Complies with 1394 OHCI 1.0 or 1.1
  • Deep transmit/receive FIFO's
    • 8 Kbyte isochronous transmit FIFO.
    • 4 Kbyte asynchronous transmit FIFO.
    • 8 Kbyte isochronous receive FIFO.
    • 8 Kbyte asynchronous receive FIFO.
  • Eight(8) isochronous transmit/receive contexts
  • Two external and One Internal FireWire ports
  • Low Profile PCI Form Factor (BR-00194)
The FW-PCIE1X20 is a 3 port FireWire (IEEE 1394a) to PCI Express Host Adapter.

The FW-PCIE1X20 combines an OHCI (Open Host Controller Interface) and a high-performance, standards-compliant PCI Express 1.1 host system interface to provide S400 1394a-2000 compliant throughput in a small PCB (Printed Circuit Board) and low power dissipation.

MultipleVCs (Virtual Channels) on the PCI Express link provide native support for QoS (Quality of Service) transmission for real-time and multimedia applications in a standards-based framework, ensuring compatibility with current and future operating systems. Active-state power management allows dynamic power management during periods of reduced network activity.

Technical Specifications
PCI Express:
  • Full compliance with PCI Express revision 1.1.
  • Single-lane (x1) architecture.
  • Multiple virtual channel (VC0,VC1 ) support fordiffe-rentiating 1394 isochronous traffic.
  • Eight user-programmable traffic classes.
  • Interrupts through legacy INTx interface or message signaled interrupt (MSI).
  • 64-bit and 32-bit platform support.
  • Supports PCI Express clock power management viaCLKREQN signal for form factors that support thisprotocol.
  • Supports all linkpowermanagement states (L0,L0s,L1,andL2/L3) and active state power management(ASPM).
  • Supports wake-up from a low-power state via in-bandbeacon signaling and side-band WAKE_N signal.
OHCI (Open Host Controller Interface)
  • Pipelined processing enables descriptor fetch, data fetch, transmit, and descriptor status update to operate in parallel for asynchronous transmit (AT).
  • All descriptors for a block transfer fetched from system memory in one PCIe transfer.
  • OHCI 1.0 backwards-compatible:
  • Configurable via EEPROM to operate in either
    OHCI 1.0 or OHCI 1.1 mode.
  • Isochronous receive dual-buffer mode.
  • Enhanced isochronous transmit skip/overflow.
  • ack_data_error improvements for asynchronous and physical requests.
  • Enhanced configuration status register (CSR)implementation.
  • Autonomous configuration ROM update.
  • Enhanced power management support, including ack_tardy event.
  • Enhanced self-ID protocol, including selfIDComplete2 event.
  • Compatible with Microsoft Windows and MacOS operating systems.
  • 8 KB isochronous transmit FIFO.
  • 4 KB asychronous transmit FIFO.
  • 8 KB isochronous receive FIFO.
  • 8 KB asynchronous receive FIFO.
  • Dedicated asynchronous and isochronous descriptor-based direct memory access (DMA) engines.
  • Eight isochronous transmit contexts.
  • Eight isochronous receive contexts.
  • Prefetches isochronous transmit data.
  • Posted write transactions.
  • Parallel processing of incoming physical read and write requests.
  • Notification (via interrupt) of a failed register access.
  • Support for up to 48-bit addressing per OHCI specification for the physical DMA transfers.
  • Physical upper bound register.
  • Fairness control register.
  • Support for multiple outstanding requests at DMAs.
  • Segmenting of transfers into PCI Express-sized requests.
1394a-2000 Link
  • Support for calculation and checking of the cyclic redundancy check (CRC) on outgoing and incoming packets.
  • Support for decoding the destination ID of incoming 1394 packets to determine if an acknowledge is needed.
  • Cycle master and isochronous resource manager capability.
  • Support for 1394a-2000 acceleration features.
1394a-2000 PHY
  • Three IEEE 1394a-2000 compliant ports supporting IEEE 1394a-2000 speeds of 100 Mb/s, 200 Mb/s, and 400 Mb/s over 4.5 m copper.
  • Full support for IEEE 1394a-2000 and 1394-1995 standard provisions for high-performance serial bus.
  • Registers to indicate power class modes.
  • Extended BIAS_HANDSHAKE time for enhanced interoperability with camcorders.
  • While unpowered and connected to the bus, the device does not drive TPBIAS on a connected port even if receiving incoming bias voltage on that port.
  • No need for an external filter capacitor for PLL.
  • Link-on as a part of the internal PHY core-link interface.
  • Arbitrated short bus reset.
  • Ack-accelerated arbitration and fly-by concatenation.
  • Connection debounce.
  • Multispeed packet concatenation.
  • PHY pinging and remote PHY access packets.
  • Port disable/suspend/resume.
  • PHY-link interface initialization and reset.
  • Support for the 1394a-2000 register set.
  • Fully interoperable with Firewire® and i.LINK® implementation of IEEE 1394-1995.
  • Cable power fail interrupt reported when voltage at TPCPS pin falls below 7.5 V.
  • Separate cable bias and driver termination voltage supply for each port provided.
Number of Ports:
  • Two External FireWire 6pin ports
  • One Internal FireWire 6pin port
Bus Power Connector:
  • Big IDE 4-pin DC Power Connector
Available Models
Operating System Requirements
  • Windows 2000/XP , Windows Server 2003 and Windows Vista/7
  • Mac OS 10.4.8 or later
  • Linux 2.6.X
  • CE Test: Pass
  • FCC Test : Pass


Packing list
Packing Type
Carton size
Bulk Packing
CT-00008 58*44*23cm
Bulk Packing
CT-00008 58*44*23cm
*G.W. tolerance ±0.5kg