- Full compliance with PCI Express revision 1.1.
- Single-lane (x1) architecture.
- Multiple virtual channel (VC0,VC1 ) support fordiffe-rentiating
1394 isochronous traffic.
- Eight user-programmable traffic classes.
- Interrupts through legacy INTx interface or message signaled interrupt (MSI).
- 64-bit and 32-bit platform support.
- Supports PCI Express clock power management viaCLKREQN signal for form factors that support thisprotocol.
- Supports all linkpowermanagement states (L0,L0s,L1,andL2/L3) and active state power management(ASPM).
- Supports wake-up from a low-power state via in-bandbeacon signaling and side-band WAKE_N signal.
|OHCI (Open Host Controller Interface)
- Pipelined processing enables descriptor fetch, data fetch, transmit, and descriptor status update to operate in parallel for asynchronous transmit (AT).
- All descriptors for a block transfer fetched from system memory in one PCIe transfer.
- OHCI 1.0 backwards-compatible:
- Configurable via EEPROM to operate in either
OHCI 1.0 or OHCI 1.1 mode.
- Isochronous receive dual-buffer mode.
- Enhanced isochronous transmit skip/overflow.
- ack_data_error improvements for asynchronous and physical requests.
- Enhanced configuration status register (CSR)implementation.
- Autonomous configuration ROM update.
- Enhanced power management support, including ack_tardy event.
- Enhanced self-ID protocol, including selfIDComplete2 event.
- Compatible with Microsoft Windows and MacOS operating systems.
- 8 KB isochronous transmit FIFO.
- 4 KB asychronous transmit FIFO.
- 8 KB isochronous receive FIFO.
- 8 KB asynchronous receive FIFO.
- Dedicated asynchronous and isochronous descriptor-based direct memory access (DMA) engines.
- Eight isochronous transmit contexts.
- Eight isochronous receive contexts.
- Prefetches isochronous transmit data.
- Posted write transactions.
- Parallel processing of incoming physical read and write requests.
- Notification (via interrupt) of a failed register access.
- Support for up to 48-bit addressing per OHCI specification for the physical DMA transfers.
- Physical upper bound register.
- Fairness control register.
- Support for multiple outstanding requests at DMAs.
- Segmenting of transfers into PCI Express-sized requests.
- Support for calculation and checking of the cyclic redundancy check (CRC) on outgoing and incoming packets.
- Support for decoding the destination ID of incoming 1394 packets to determine if an acknowledge is needed.
- Cycle master and isochronous resource manager capability.
- Support for 1394a-2000 acceleration features.
- Three IEEE 1394a-2000 compliant ports supporting IEEE 1394a-2000 speeds of 100 Mb/s, 200 Mb/s, and 400 Mb/s over 4.5 m copper.
- Full support for IEEE 1394a-2000 and 1394-1995 standard provisions for high-performance serial bus.
- Registers to indicate power class modes.
- Extended BIAS_HANDSHAKE time for enhanced interoperability with camcorders.
- While unpowered and connected to the bus, the device does not drive TPBIAS on a connected port even if receiving incoming bias voltage on that port.
- No need for an external filter capacitor for PLL.
- Link-on as a part of the internal PHY core-link interface.
- Arbitrated short bus reset.
- Ack-accelerated arbitration and fly-by concatenation.
- Connection debounce.
- Multispeed packet concatenation.
- PHY pinging and remote PHY access packets.
- Port disable/suspend/resume.
- PHY-link interface initialization and reset.
- Support for the 1394a-2000 register set.
- Fully interoperable with Firewire® and i.LINK® implementation of IEEE 1394-1995.
- Cable power fail interrupt reported when voltage at TPCPS pin falls below 7.5 V.
- Separate cable bias and driver termination voltage supply for each port provided.
|Number of Ports:
- Two External FireWire 6pin ports
- One Internal FireWire 6pin port
|Bus Power Connector:
- Big IDE 4-pin DC Power Connector