QU3IP4X-PCIE8XG201 Quad Channel 4-port USB 3.0 & Internal PCIe x4 (Dual x2) to PCIe x8 Gen 2 Host Card

Highlights

Host Bus: PCIe x8 Gen 2 (40.0 Gb/s)
- Compliant with PCI Express Base Specification Revision 2.0
Four independent USB 3.0 Host Controllers

Compliant with Universal Serial Bus 3.0 specification Revision 1.0
Compliant with Intel’s eXtensible Host Controller Interface (xHCI) specification Revision 1.0
Each USB 3.0 Host Controller supports one downstream port

Four USB 3.0 Cable Ports (A-type Receptacle)
- Provides USB 3.0 cable port lock mechanism

Introduction

QU3IP4X-PCIE8XG201 is Quad Channel 4-port (1-port x 4) USB 3.0 & Internal PCIe x4 (x4 or four x1) to
PCIe x8 Gen 2 Host Card.
The flexible hardware configuration allows the switch to be tailored for the following configuration options:

Technical Specifications

Upstream PCIe interface	8-lane PCI Express PCIe Gen 1 (2.5GT/s) PCIe Gen 2 (5.0GT/s)
Downstream Port interface	Four independent USB 3.0 Cable Ports (A-type Receptacle) Two IOI Proprietary Dual-lane Internal PCIe Ports (PCIe-1~2) 10X2_19pin Header (Pitch=2.0mm) 2-lane PCIe Each Dual-lane Internal PCIe Port PCIe Gen 1 (2.5GT/s) PCIe Gen 2 (5.0GT/s)
USB Features	Compliant with USB 3.0 Specification Revision 1.0 Compliant with Intel’s eXtensible Host Controller Interface (xHCI) specification Revision 1.0 Each USB port supporting SS/HS/FS/LS data rates (5Gbps/480Mbps/12Mbps/1.5Mbps)
USB Data Transfer Rate	Low-speed (1.5 Mbps) Full-speed (12.0 Mbps) High-speed (480.0 Mbps) Super-speed (5.0 Gbps)
USB Bus Power Input (5V & 12V)	Either Big IDE 4-pin DC Power Connector or/and SATA 15pin Power Connector
PCIe Features	Standards Compliant PCI Express Base Specification r2.0 (Backwards compatible with PCIe r1.0a/1.1) PCI Power Management Spec r1.2 Microsoft Vista Compliant Supports Access Control Services Dynamic link-width control Dynamic SerDes Speed Control High Performance Non-blocking internal architecture Full line rate on all ports Cut-Thru latency: 140ns Maximum Payload Size - 2,048 bytes Read Pacing (intelligent bandwidth allocation) Dual Cast Dynamic Buffer Pool Architecture for faster credit updates PCI Express Power Management Link power management states: L0, L0s, L1, L2/L3 Ready, and L3 (with Vaux *not supported*) Device power management states: D0 and D3hot Active State Power Management (ASPM) Quality of Service (QoS) Two Virtual Channels (VC) per port Eight Traffic Classes per port Weighted Round-Robin Port & VC Arbitration
Lane Status LEDs Blink: Gen 1 speed Solid: Gen 2 speed	Upstream Lane Status LEDs UPCIe LED1: Upstream x1 Status LED UPCIe LED4: Upstream x4 Status LED UPCIe LED8: Upstream x8 Status LED Downstream Lane Status LEDs PCIe-1L8: Downstream Lane 8 Status LED PCIe-1L9: Downstream Lane 9 Status LED PCIe-2L10: Downstream Lane 10 Status LED PCIe-2L11: Downstream Lane 11 Status LED
Jumper J5 (PCIe1~2) (PCIe Port Configuration)	Pin1-2: x8, x4, x1, x1, x1, x1 Pin2-3: x8, x1, x1, x1, x1, x1, x1, x1, x1
Computer Platform Requirements	Desktop computer equipped with a PCIe 1.0/2.0 x8, x16 slot

Computer Platform

Computer with PCI Express slot ( x8, x16)

Note:
For the best performance (5.0 Gbps), It should be installed in a PCIe Gen 2 compliant slot in the host computer. Most computers have PCIe Gen 2 (5.0 Gbps) throughput on x8 or x16 slots.
A PCIe Gen 1 compliant slot reaches up to 2.5 Gbps throughput

Operating System Requirements